Conventionally, a high-efficiency power amplifier described above is categorized into the following arrangements: (i) an arrangement in which an amplitude of a signal is adjusted in a signal source, and (ii) an arrangement in which an amplitude of a signal is adjusted in an amplifier section for amplifying a 1-bit digital signal that has been subjected to digital sigma modulation. FIG. 8 shows a high-efficiency power amplifier having the former arrangement, and FIG. 9 shows a high-efficiency power amplifier having the latter arrangement.
In the arrangements shown in FIG. 8 and FIG. 9, a digital audio signal that has been outputted from a digital signal source 101 is subjected to ΔΣ modulation by means of a ΔΣ modulation circuit 102, so that thus modulated signal becomes a 1-bit digital signal, and is supplied to a gate drive circuit 103. The gate drive circuit 103 outputs a gate drive signal on the basis of the 1-bit digital signal, and drives a power MOSFET constituting an output full-bridge circuit 104. In the output full-bridge circuit 104, it is possible to obtain the 1-bit digital signal, that has been subjected to power amplification, in accordance with a switching operation of the power MOSFET. Then, the 11-bit digital signal that has been amplified is converted into an analog audio signal after passing through a low pass filter 105, and thus converted signal is outputted as a sound by an output device 106 such as a head phone.
In an arrangement of FIG. 8, due to an amplitude adjusting signal supplied by a micro computer 107, the digital signal source 101 controls an amplitude of the audio signal for each volume step. Further, in the output full-bridge circuit 104, a constant power source voltage is supplied from a fixed-voltage power source 108 to a power source terminal of the output full-bridge circuit 104, so that the 1-bit digital signal is not subjected to amplitude adjustment.
Japanese Unexamined Patent Publication No. 332553/2000 (Tokukai 2000-332553)(Publication date: Nov. 30, 2000) relates to the arrangement of FIG. 8. In a 1-bit digital amplifier recited in this document, a digital audio signal or an analog audio signal is varied as an input signal by a level control device. However, the 1-bit digital amplifier is different from the arrangement of FIG. 8 in that: a difference between a signal whose amplitude level has been changed and a feedback signal that has been negatively fed-back from a pulse amplifier via a feedback circuit is quantized by a ΔΣ modulation section as 1 bit.
Meanwhile, in an arrangement of FIG. 9, the digital signal source 101 does not adjust an amplitude of an audio signal, but a power source voltage of a variable voltage power source 109 is controlled for each step of setting the volume in accordance with an analog power source control voltage supplied by the micro computer 107. Thus, in the output full-bridge circuit 104, a variable power source voltage controlled by a fixed-voltage power source 109 is provided to a power source terminal of the output full-bridge circuit 104, so that the 1-bit digital signal is subjected to amplitude adjustment.
In an arrangement of FIG. 9, as shown by Δ of FIG. 10, an amplitude level (input level) of an input signal from the digital signal source 101 is constant, and as shown by ▭ and ⋄, a level of a power source voltage of the variable voltage power source 109 and an amplitude level (output level) of an output of the output full-bridge circuit 104 vary substantially in the same manner.
Note that, a document relating to the arrangement of FIG. 9 was not found.
FIG. 11 is a block diagram showing an arrangement of a conventional digital amplifier 201 as a high-efficiency amplifier having an arrangement similar to the arrangement of FIG. 9.
The digital amplifier 201 converts an analog sound signal into a 1 bit digital signal by a ΔΣ block 202, and performs power amplification (amplitude conversion) with respect to the 1 bit digital signal, and low pass filters 203 and 204 convert the 1 bit digital signal into an analog signal, thereby performing power amplification with high efficiency as described above. In an output drive circuit 205, the power amplification is performed by causing (i) a series circuit of output transistors Q201 and Q202 each of which is constituted of NMOSFET intervening between a high-level power source line 206 and a low-level power source line 207 and (ii) a series circuit of output transistors Q203 and Q204 each of which is constituted of NMOSFET intervening between the high-level power source line 206 and the low-level power source line 207 to perform a push-pull operation. The output transistors Q201 to Q204 operate in a saturation range, so that it is possible to perform power amplification with high efficiency as described above.
Thus, a 1-bit signal supplied from the ΔΣ block 202 is inputted to an upper gate drive circuit 208, and the output transistors Q201 and Q203 are driven by a positive phase component and a negative phase component that are generated here. The other 1-bit signal from the ΔΣ block 202 is inputted to a lower gate drive circuit 209, and the output transistors Q202 and Q204 are driven by a positive phase component and a negative phase component that are generated here. By the gate drive circuits 208 and 209, a combination of the output transistors Q201 and Q204 that are positioned diagonally with respect to each other is driven at the same phase, and a combination of the output transistors Q202 and Q203 is driven at the same phase, and (i) the combination of the output transistors Q201 and Q204 and (ii) the combination of the output transistors Q202 and Q203 are driven at phases opposite to each other, thereby realizing the push-pull operation.
Further, a variable direct current power source voltage V00 supplied from the variable voltage power source 210 is inputted via the power source line 206 to drains of the output transistors Q201 and Q203. Each of sources of the output transistors Q202 and Q204 has a GND level via the power source line 207. Further, (i) a junction between a source of the output transistor Q201 and a drain of the output transistor Q202 and (ii) a junction between a source of the output transistor Q203 and a drain of the output transistor Q204 function as output terminals, and are respectively connected to a positive-phase output terminal P201 and a negative-phase output terminal P202 via the low pass filters 203 and 204. A load resistor P201 is provided between the output terminals P201 and P202. The low pass filter 203 is constituted of a coil L201 and a capacitor C201, and the low pass filter 204 is constituted of a coil L202 and a capacitor C202.
Meanwhile, a PWM signal which switches between a Vcc level and a GND level is inputted from a power source input terminal T00 to a variable voltage power source 210. When the potential Vcc/GND is smoothed by a low pass filter 211 constituting the variable voltage power source 210, a voltage corresponding to a duty of the PWM signal is outputted. The voltage is inputted to the drains of the output transistors Q201 and Q203 via the power source line 206 as the power source voltage V00. When an amplitude level of an outputted digital signal is varied by varying the power source voltage V00, and the digital signal is smoothed by the low pass filters 203 and 204, it is possible to vary a level of the reproduced analog audio signal, that is, it is possible to perform volume adjustment. The low pass filter 211 is constituted of a coil L203 and a capacitor C203.
Further, a direct current power source voltage V01, supplied to a power source input terminal T01, that has been outputted from a fixed-voltage power source (not shown), is inputted to the upper gate drive circuit 208. Likewise, a direct current power source voltage V02, supplied to a power source input terminal T02, that has been outputted from the fixed-voltage power source (not shown), is inputted to the lower gate drive circuit 209.
Recently, such a high-efficient amplifier has been required to consume less power.
However, the arrangements of FIG. 8 and FIG. 9 have the following problems in terms of the power consumption.
In the arrangement of FIG. 8, even when turning down the volume, a constant voltage is supplied as a power source voltage to the output full-bridge circuit 104 which performs switching amplification with respect to an output signal from the ΔΣ modulation circuit 102, so that it is general that the power consumption in this case is not different from power consumption in case of turning up the volume (this is well-known fact, so that there is no particular data). In order to reduce the power consumption, a power source voltage of the output full-bridge circuit 104 may be reduced. However, this raises the following problem: drop of the power source voltage causes the output level to drop, so that a maximum output (maximum volume) also drops.
In the arrangement of FIG. 9, a level of the power source voltage of the variable voltage power source 109 and an amplitude level (output level) of an output of the output full-bridge circuit 104 vary substantially in the same manner, so that the power consumption is not always kept at a level of the high volume as in the arrangement of FIG. 8. However, in the arrangement of FIG. 9, it is general that the variable voltage power source 109 is arranged as a servo circuit. Thus, a sufficient servo gain cannot be obtained in case of a low voltage, so that a voltage which has not been sufficiently servoed by the servo circuit is supplied to the switching amplification means. As a result, this raises the following deterioration of an audio performance: a distortion scale factor increases; S/N drops; and remaining noise increases. A data example of the distortion scale factor at this time is shown by a graph of FIG. 5. As shown by ♦ of FIG. 5, in a range where the output volume value is small, the distortion scale factor becomes larger as an output volume value becomes smaller.
Further, in the digital amplifier 201, when turning down the volume, the duty of the PWM signal inputted to the power source input terminal TOO is reduced as described above, so that a power level actually provided to a speaker, that is, a power level consumed in the output drive circuit 205 becomes smaller. However, power consumption in other circuits is the same as power consumption in the case where the volume is high. This is the same as in the case of FIG. 9. For example, the power consumption thereof is the same as the power consumption in the gate drive circuit 103 in the case of turning down the volume.
In view of the foregoing problems, the present invention was devised to reduce the power consumption of a digital amplifier in case of turning down the volume. Further, the present invention improves an audio performance of the digital amplifier.